1. Field of the Invention
The present invention relates to a video data run length decoding apparatus, and in particular, to an improved video data run length decoding apparatus which is capable of effectively decoding a coded video data and generating a data stream using a run length of the video data.
2. Description of the Conventional Art
Generally, the video data coding technique is directed to coding and decoding video data using their run lengths. Here, the "run" represents a zero data. When a video data is discrete cosine-converted and then quantized, an original video data is converted to a zero data. At this time, consecutive zero values correspond to the number of run values. For example, if the value of a video data is 0000001, the number of the run is 6. The run length of the data to be transmitted is 61. Therefore, the number of the zero values is computed, and then only the value corresponding to the number of the same is transmitted for thereby implementing a predetermined coding effect. With the above-described coding method, the coding effect is enhanced, and the original data is not lost for thereby obtaining a good quality of the picture. The coded data is expressed by the number of the run data and the level of the same.
The value of the run is counted when coding video data and then only the number of the run data is transmitted for thereby enhancing a coding effect. When decoding the data, the data is decoded to the data having its original run value. At this time, the data is decoded by the unit of the 64 blocks.
In the run length decoding block of the conventional decoding apparatus, the coded video data is decoded to its original video data by a reverse zig zag and dequantizer and a reverse discrete cosine converter. At this time, the decoded video data should maintain a predetermined video stream based on a pipeline operation. The coded video data is consecutively computed on the pipeline. A buffer is used for storing the data because there is a difference in the data processing speed of a clock signal.
FIG. 1 illustrates the construction of a conventional video data run length decoding apparatus which includes a buffer 10 for storing a coded video data and alternately generating an interval in which there is a data and another interval in which there is not data, a decoder 20 for analyzing the run value of a video data outputted from the buffer 10 and generating a run value, a reverse zig zag and dequantizer 30 for processing the run value outputted from the run length decoder 20 based on the reverse zig zag and dequantizing method, and a reverse discrete cosine converter 40 for processing, two times, the data outputted from the reverse zig zag and dequantizing unit 30 based on the reverse discrete cosine conversion method and decoding the thusly converted data into a 2-dimensional video data.
The operation of the conventional decoding apparatus will be explained with reference to FIG. 1.
First, the buffer 10 receives coded video data and stores the same and then alternately generates an interval in which there is a data and another interval in which there is not a data. The run length decoder 20 analyzes the run value of the video data and generates a run value. The reverse zig zag and dequantizer 30 process the data outputted from the run length decoder 20 based on the reverse zig zag and dequantization operation. The reverse discrete cosine converter 40 processes the data outputted from the reverse zig zag and dequantizer 30 based on the reverse discrete cosine conversion for thereby obtaining a one-dimensional video data and then converts the one-dimensional video data based on the reverse discrete cosine conversion and the two-dimensional video data, respectively. The buffer 10 stores the coded data for implementing a process delay time which is required for converting the one-dimensional video data into a two-dimensional video data and then alternately outputs an interval in which there is a 8-clock signal data and another interval in which there is not a 8-clock signal data by the 8-clock signal unit. In the interval in which there is 8 data, the one-dimensional cosine conversion is performed for thereby obtaining a one-dimensional video data, and in the interval in which there is not 8 data, the one-dimensional video data which is processed by a pre-memory is processed based on the two-dimensional discrete cosine conversion for thereby obtaining a two-dimensional video data. According the standard recommendation such as H.263, the above-described operation is implemented based on the 8.times.8 pixel unit as a basic block. In addition, in order to efficiently implement the hardware, the two-dimensional discrete cosine conversion is computed by using twice the reverse discrete cosine converter 40.
As described above, in the conventional video data run length decoding apparatus, when decoding the coded video data, the buffer (memory) is required for storing the coded data inputted for implementing a predetermined processing delay time which is required for converting the one-dimensional video data into the two-dimensional video data using the reverse discrete cosine converter. Therefore, the layout area is increased due to the memory and an additional control circuit. There is a limit for implementing a high speed system.